Conventional memory controllers for high-speed memory devices such as Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) integrated circuit devices allow for fast data storage and retrieval. However, conventional memory controllers for DDR SDRAM devices have high power consumption.
The SSTL18 interface, as specified in the JESD-15 standard, published by the Joint Electron Device Engineering Council, specifies the operating requirements for DDR2 SDRAM memory devices. Memory controllers for operating DDR2 SDRAM devices provide inputs to each DDR2 SDRAM device to be operated and outputs from each DDR2 SDRAM device that fully meet the SSTL18 interface requirements to assure that the memory controller will operate correctly with any DDR2 SDRAM device.
In many systems there is a need for low cost memory. Because of economies of scale, DDR2 SDRAM devices are the least expensive option for such systems. Thus, many systems that do not require high speed operation utilize DDR2 SDRAM memory and operate the DDR2 SDRAM memory at the lowest allowed speed in the SDRAM's data sheet specifications, which is 125 MHz. This provides good results for many applications. However, some applications also require low power consumption.
For systems that require low cost memory and low power consumption, there is a need for a memory controller having reduced power consumption as compared to conventional DDR2 SDRAM memory controllers. Much of the power consumed by conventional memory controllers is consumed by the many input buffers that interface with DDR2 SDRAMs. More particularly, since differential input buffers are required to meet the small input swing required to meet the Vil (max) and Vih (min) threshold defined in the SSTL18 interface standard, conventional memory controllers utilize differential input buffers, with one side of the differential input buffer tied to the reference voltage (Vref) and the other side connected to the SSTL18 signal line. For example, in a conventional memory controller manufactured by Xilinx Inc. of San Jose, Calif. that includes a Spartan-3A Field Programmable Gate Array (FPGA) integrated circuit device configured with a “MAC” memory controller for controlling DDR2 SDRAM devices, each input buffer consumes about 2 mA of static current from a 3.3 volt VccAux power rail. Accordingly, a 72-bit DDR2 SDRAM interface with 90-bi-directional SSTL18 IO will consume about 600 mW of static power, which is more than half of the total power consumed by the entire memory controller design.
Accordingly there is a need for a memory controller having reduced static power requirements. In addition, there is a need for a method and apparatus that will allow for control of DDR2 SDRAM devices that has reduced power requirements.